Recently, an ADPLL (All Digital PLL) circuit in which all control signals of a PLL (Phase Locked Loop) circuit are digitized is used in a wireless communication device such as a wireless LAN device. In the ADPLL circuit, an analog circuit is replaced by a digital circuit, so that space saving and power saving can be attained due to progress in a process.
The ADPLL circuit includes a digital loop filter, a DCO (Digitally-Controlled Oscillator), a counter, and a TDC (Time-to-Digital Converter). The counter counts an output CKV of the DCO, and outputs a count value based upon a reference signal that is synchronized by the output CKV of the DCO. The TDC takes out a phase difference of not more than 1 cycle of the output from the DCO in synchronism with the reference signal REF. A result of a comparison (difference) between the value obtained by adding the count value and the phase difference and a phase control signal is given to the digital loop filter. The oscillating frequency of the DCO is controlled based upon the output from the digital loop filter.
In the ADPLL described above, the above-mentioned TDC is inevitable in order to reduce the impact of discretization and enhance phase noise characteristic of the output CKV. In general, the TDC frequently uses a circuit that utilizes a delay element in order to obtain phase information having high resolution. The delay amount is not constant, and the obtained delay information has to be normalized for 1 cycle of the oscillating frequency in order to make the delay amount a value that can be utilized in the digital circuit (e.g., see “Robert Bogdan Staszewski, et. al, “All-Digital PLL and Transmitter for Mobile Phones”, IEEE JOURNAL OF SOLID-STATE CIRCUITES, VOL. 40, NO. 12, DECEMBER 2005”).
However, since the TDC having the normalization circuit has great power consumption and a large area, it is desired to constitute the ADPLL without using the TDC.
In “Werner Grollitsch, Roberto Nonis, Nicola Da Dalt “26.6 A 1.4 psrms-Period-Jitter TDC-less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65 nm CMOS”, 2010 IEEE International Solid-State Circuits Conference”, the TDC-less ADPLL is proposed. It also proposes a method of generating fine phase information without changing an oscillating frequency, by increasing a delay stage of an LC oscillator in an ADPLL of TDC-integration type using a ring oscillator.
However, in the structure of the LC oscillator and a frequency divider as described in the above-mentioned document, the oscillating frequency has to be increased with respect to a necessary phase interval. Therefore, increasing the oscillating frequency only to obtain the finer phase interval increases power consumption.